Koren and Koren : Incorporating Yield Enhancement into the Floorplanning Process

Incorporating Yield Enhancement into the Floorplanning Process

ÐThe traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in add...

Yield and Routing Objectives in Floorplanning

Traditionally the oorplan of a chip has been determined so as to minimize the total chip area and reduce the routing costs. Recently, it has been shown that the oorplan also a ects the yield of the chip. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a oorplan. The goal of this paper is to study the two seemingly disjoint ob...

On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits1

Constructive floorplanning with a yield objective

The ability to improve the yield of integrated circuits through layout modification has been recognized, and several techniques for yield enhanced routing and compaction have been developed. Still, yield issues are rarely a factor in the choice of the floorplan mainly due to the tendency to focus on the more important timing and area objectives. Consequently, floorplanning tools have been devel...

On the effect of floorplanning on the yield of large area integrated circuits

{ Until recently, VLSI designers rarely considered yield issues when selecting a oorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the oorplan can aaect the projected yield. We study several general oorplan structures, make some speciic recommendations, and apply them to actual VLSI chips...